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A `!vision processing unit`! (`!VPU`!) is (as of 2023) an emerging class of `F33f`_`[microprocessor`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microprocessor]`_`f; it is a specific type of `F33f`_`[AI accelerator`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AI_accelerator]`_`f, designed to `F33f`_`[accelerate`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Hardware_acceleration]`_`f `F33f`_`[machine vision`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Machine_vision]`_`f tasks.`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f]`:cite-ref-2[`F5bf`_`[2`#cite-note-2]`_`f]

>>Contents

• `F0af`_`[Overview`#overview]`_`f

• `F0af`_`[Contrast with GPUs`#contrast-with-gpus]`_`f

• `F0af`_`[Examples`#examples]`_`f

• `F0af`_`[Broader category`#broader-category]`_`f

• `F0af`_`[See also`#see-also]`_`f

• `F0af`_`[References`#references]`_`f

• `F0af`_`[External links`#external-links]`_`f

-─

>>Overview

Vision processing units are distinct from `F33f`_`[graphics processing units`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Graphics_processing_unit]`_`f (which are specialised for `F33f`_`[video encoding and decoding`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Video_codec]`_`f) in their suitability for running `F33f`_`[machine vision algorithms`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Machine_vision]`_`f such as CNN (`F33f`_`[convolutional neural networks`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Convolutional_neural_network]`_`f), SIFT (`F33f`_`[scale-invariant feature transform`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Scale-invariant_feature_transform]`_`f) and similar.

They may include `F33f`_`[direct interfaces`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Interface_(computing)]`_`f to take data from `F33f`_`[cameras`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Digital_cameras]`_`f (bypassing any off chip buffers), and have a greater emphasis on on-chip `F33f`_`[dataflow`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Dataflow]`_`f between many `F33f`_`[parallel execution units`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Parallel_execution_units]`_`f with `F33f`_`[scratchpad memory`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Scratchpad_memory]`_`f, like a `F33f`_`[spatial architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Spatial_architecture]`_`f or a `F33f`_`[manycore`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Manycore_processor]`_`f `F33f`_`[DSP`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Digital_signal_processor]`_`f. But, like video processing units, they may have a focus on `F33f`_`[low precision`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Low_precision]`_`f `F33f`_`[fixed point arithmetic`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Fixed_point_arithmetic]`_`f for `F33f`_`[image processing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Image_processing]`_`f.

>>Contrast with GPUs

They are distinct from `F33f`_`[GPUs`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GPU]`_`f, which contain specialised hardware for `F33f`_`[rasterization`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Rasterization]`_`f and `F33f`_`[texture mapping`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Texture_mapping]`_`f (for `F33f`_`[3D graphics`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=3D_graphics]`_`f), and whose `F33f`_`[memory architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Memory_architecture]`_`f is optimised for manipulating `F33f`_`[bitmap images`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bitmap_images]`_`f in `F33f`_`[off-chip memory`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Off-chip_memory]`_`f (reading `F33f`_`[textures`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Texture_map]`_`f, and modifying `F33f`_`[frame buffers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Frame_buffers]`_`f, with `F33f`_`[random access patterns`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Locality_of_reference]`_`f). VPUs are optimized for performance per watt, while GPUs mainly focus on absolute performance.

Target markets are `F33f`_`[robotics`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Robotics]`_`f, the `F33f`_`[internet of things`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Internet_of_things]`_`f (IoT), new classes of `F33f`_`[digital cameras`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Digital_cameras]`_`f for `F33f`_`[virtual reality`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Virtual_reality]`_`f and `F33f`_`[augmented reality`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Augmented_reality]`_`f, `F33f`_`[smart cameras`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Smart_camera]`_`f, and integrating machine vision acceleration into `F33f`_`[smartphones`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Smartphone]`_`f and other `F33f`_`[mobile devices`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Mobile_devices]`_`f.

>>Examples

• `F33f`_`[Movidius Myriad X`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Movidius_Myriad_X]`_`f, which is the third-generation vision processing unit in the Myriad VPU line from `F33f`_`[Intel Corporation`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Intel]`_`f.`:cite-ref-3[`F5bf`_`[3`#cite-note-3]`_`f]

• `F33f`_`[Movidius Myriad 2`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Movidius_Myriad_2]`_`f, which finds use in `F33f`_`[Google Project Tango`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Google_Project_Tango]`_`f,`:cite-ref-riseofvpus-4-0[`F5bf`_`[4`#cite-note-riseofvpus-4]`_`f] `F33f`_`[Google Clips`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Google_Clips]`_`f and DJI drones`:cite-ref-5[`F5bf`_`[5`#cite-note-5]`_`f]

• `F33f`_`[Pixel Visual Core`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Pixel_Visual_Core]`_`f (PVC), which is a fully programmable `F33f`_`[Image`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Image_processor]`_`f, Vision and `F33f`_`[AI`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AI_accelerator]`_`f processor for mobile devices

• `F33f`_`[Microsoft HoloLens`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microsoft_HoloLens]`_`f, which includes an accelerator referred to as a `*holographic processing unit`* (complementary to its CPU and GPU), aimed at interpreting camera inputs, to accelerate environment tracking and vision for augmented reality applications.`:cite-ref-6[`F5bf`_`[6`#cite-note-6]`_`f]

• `F33f`_`[Eyeriss`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Eyeriss]`_`f, a `F33f`_`[spatial architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Spatial_architecture]`_`f designed from `F33f`_`[MIT`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=MIT]`_`f intended for running `F33f`_`[convolutional neural networks`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Convolutional_neural_network]`_`f.`:cite-ref-7[`F5bf`_`[7`#cite-note-7]`_`f]

• NeuFlow, a design by `F33f`_`[Yann LeCun`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Yann_LeCun]`_`f (implemented in `F33f`_`[FPGA`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=FPGA]`_`f) for accelerating `F33f`_`[convolutions`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Convolutions]`_`f, using a dataflow architecture.

• Mobileye EyeQ, by `F33f`_`[Mobileye`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Mobileye]`_`f

• Programmable Vision Accelerator (PVA), a 7-way VLIW Vision Processor designed by `F33f`_`[Nvidia`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Nvidia]`_`f.

>>Broader category

Some processors are not described as VPUs, but are equally applicable to machine vision tasks. These may form a broader category of `F33f`_`[AI accelerators`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AI_accelerator_(computer_hardware)]`_`f (to which VPUs may also belong), however as of 2016 there is no consensus on the name:

• `F33f`_`[IBM`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM]`_`f `F33f`_`[TrueNorth`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=TrueNorth]`_`f, a `F33f`_`[neuromorphic`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Neuromorphic]`_`f processor aimed at similar sensor data `F33f`_`[pattern recognition`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Pattern_recognition]`_`f and intelligence tasks, including video/audio.

• `F33f`_`[Qualcomm Zeroth Neural processing unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Qualcomm_Zeroth_Neural_processing_unit]`_`f, another entry in the emerging class of sensor/AI oriented chips.`:cite-ref-8[`F5bf`_`[8`#cite-note-8]`_`f]

• All models of Intel `F33f`_`[Meteor Lake`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Meteor_Lake]`_`f processors have a `F33f`_`[Versatile Processor Unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Versatile_Processor_Unit]`_`f (VPU) built-in for accelerating `F33f`_`[inference`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Statistical_inference]`_`f for computer vision and deep learning.`:cite-ref-9[`F5bf`_`[9`#cite-note-9]`_`f]

>>See also

• `F33f`_`[Adapteva Epiphany`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Adapteva_Epiphany]`_`f, a manycore processor with similar emphasis on on-chip dataflow, focussed on 32-bit floating point performance

• `F33f`_`[CELL`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=CELL]`_`f, a multicore processor with features fairly consistent with vision processing units (SIMD instructions & datatypes suitable for video, and on-chip DMA between scratchpad memories)

• `F33f`_`[Coprocessor`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Coprocessor]`_`f

• `F33f`_`[Graphics processing unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Graphics_processing_unit]`_`f, also commonly used to run vision algorithms. NVidia's Pascal architecture includes FP16 support, to provide a better precision/cost tradeoff for AI workloads

• `F33f`_`[MPSoC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=MPSoC]`_`f

• `F33f`_`[OpenCL`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=OpenCL]`_`f

• `F33f`_`[OpenVX`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=OpenVX]`_`f

• `F33f`_`[Physics processing unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Physics_processing_unit]`_`f, a past attempt to complement the CPU and GPU with a high throughput accelerator

• `F33f`_`[Tensor Processing Unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Tensor_Processing_Unit]`_`f, a chip used internally by Google for accelerating AI calculations

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f `:citerefseth-colanermatthew-humrick2016`aSeth Colaner; Matthew Humrick (January 3, 2016). "A third type of processor for AR/VR: Movidius' Myriad 2 VPU". `*Tom's Hardware`*.

`:cite-note-2`!2.`! `F0af`_`[↑`#cite-ref-2]`_`f `:citerefprasid-banerje2016`aPrasid Banerje (March 28, 2016). "The rise of VPUs: Giving Eyes to Machines". `*Digit.in`*.

`:cite-note-3`!3.`! `F0af`_`[↑`#cite-ref-3]`_`f "Intel® Movidius™ Vision Processing Units (VPUs)". `*Intel`*.

`:cite-note-riseofvpus-4`!4.`! `F0af`_`[↑`#cite-ref-riseofvpus-4-0]`_`f `:citerefweckler2016`aWeckler, Adrian (14 February 2016). "Dublin tech firm Movidius to power Google's new virtual reality headset". `*Independent.ie`*. Retrieved 15 March 2016.

`:cite-note-5`!5.`! `F0af`_`[↑`#cite-ref-5]`_`f "DJI Brings Two New Flagship Drones to Lineup Featuring Myriad 2 VPUs - Machine Vision Technology - Movidius". `*www.movidius.com`*.

`:cite-note-6`!6.`! `F0af`_`[↑`#cite-ref-6]`_`f `:citereffred-o-connor2015`aFred O'Connor (May 1, 2015). "Microsoft dives deeper into HoloLens details: 'Holographic processor' role revealed". `*PCWorld`*.

`:cite-note-7`!7.`! `F0af`_`[↑`#cite-ref-7]`_`f `:citerefchen-yu-hsinkrishna-tusharemer-joelsze-vivienne2016`aChen, Yu-Hsin; Krishna, Tushar; Emer, Joel & `F33f`_`[Sze, Vivienne`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Vivienne_Sze]`_`f (2016). "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks". `*IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers`*. pp. 262–263.

`:cite-note-8`!8.`! `F0af`_`[↑`#cite-ref-8]`_`f "Introducing Qualcomm Zeroth Processors: Brain-Inspired Computing". `*Qualcomm`*. October 10, 2013.

`:cite-note-9`!9.`! `F0af`_`[↑`#cite-ref-9]`_`f "Intel to Bring a 'VPU' Processor Unit to 14th Gen Meteor Lake Chips". `*PCMAG`*. August 2022.

>>External links

• Eyeriss architecture

• Holographic processing unit

• NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision Archived 2017-05-05 at the `F33f`_`[Wayback Machine`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Wayback_Machine]`_`f

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